Semiconductor memory devices are subject to defects that may cause some memory cells to be read with incorrect data. For example, in high-density Read-Only-Memory (ROM) devices, a very common defect is a contact window or “via” in the conduction path of a cell transistor being open or nonconductive when it should be conductive. Another defect which is becoming much more prevalent is a “weak” bit defect, which is a bit cell with very poor drive strength. An open via or weak bit defect typically causes the associated bit line to remain at a precharge level when it should be discharged. The result is that the data read from this bit line is incorrect. Defects of the type described above are generally discovered during post-manufacture testing of integrated circuit memory devices. Defective memory devices may need to be discarded, thereby reducing the yield of the integrated circuit manufacturing process, and increasing the net manufacturing costs for the non-defective devices.
A number of techniques are known for addressing defects in memory devices. One such technique involves incorporating redundant lines, rows or blocks of cells into the device. This allows lines, rows or blocks having defective cells to be replaced with corresponding non-defective redundant elements. The replacement may be controlled, by way of example, using a volatile switch, such as a latch or flip-flop, or a non-volatile switch, such as a laser-activated fuse or electronically programmable memory element.
Another technique for addressing defects in memory devices involves utilizing an error correction code to correct data errors attributable to defects. Examples of this type of approach are disclosed in U.S. Patent Application Publication No. 2006/0048031, entitled “Built-In Self-Test for Memory Arrays Using Error Correction Coding,” which is commonly assigned herewith and incorporated by reference herein.
Conventional approaches based on use of redundant elements or error correction codes may exhibit certain drawbacks. For example, such approaches may lead to undesirable increases in the size of the memory device, or in memory access and cycle times.
Accordingly, a need exists for an improved approach to dealing with defects in memory devices, particularly the common via or weak bit defects which are typical in high-density ROM devices.